This invention relates to MOS gated semiconductor devices and more specifically relates to a novel superjunction type semiconductor device structure in which each of a plurality of trenches have a plurality of longitudinally extending opposite conductivity regions which act to deplete one another during voltage blocking operation.
Superjunction devices are well known, such as devices shown in copending application Ser. No. 09/732,401, filed Dec. 7, 2000 entitled HIGH VOLTAGE VERTICAL CONDUCTION SUPERJUNCTION SEMICONDUCTOR DEVICE in the name of Daniel M. Kinzer and Srikant Sridevan (IR-1756). In these devices, a plurality of spaced parallel vertical conduction regions or pedestals of one conductivity type extend vertically through a wafer of semiconductor material of the other conductivity type. A conventional DMOS type of structure may be used to turn the device on and off between a top source electrode and a bottom drain electrode. The concentrations and lateral dimensions and spacings of the vertical conduction regions is designed so that when blocking voltage is applied between the drain and source electrodes, the vertical N and P regions each fully deplete to prevent conduction. However, when conduction is desired, it can take place through the undepleted drift regions which are connected to the source electrode by a suitable MOS gate structure. These regions can have a higher concentration than that needed in the conventional vertical conduction MOSFET because its concentration is no longer related to a low concentration needed for a given blocking voltage. Consequently, superjunction devices will generally have a lower RDSON than the conventional MOSFET which requires a higher resistivity body or substrate to block voltage.
Superjunction devices also usually require a complex termination structure surrounding the active area because the wafer body has a relatively high concentration. Thus, it is more difficult to deplete the high concentration termination region as with conventional diffusion rings which are used in low resistivity epitaxial layers of prior art power MOSFETs.
It has been found that the performance characteristics of the superjunction device described above are very sensitive to processing conditions. Thus, the cell dimensions must be precisely controlled; the concentration of the N and P depletion regions must be very carefully controlled, and the design and processing of the termination region is very complex. It would be desirable to produce a superjunction device which is less dependent on precise processing conditions and which can also employ a simple termination.
In accordance with the invention a novel structure is provided in which the sidewalls of vertical trenches are doped by alternating N and P stripes which extend from top to bottom of the trenches, and which are self-compensating. Thus, the alternate N and P stripes act to deplete one another during blocking while only one set of the stripes, for example, the N stripes are connected to a source electrode and conduct when the device is turned on.
More specifically, parallel spaced and symmetrically disposed vertical cylindrical wells are etched in a highly resistive, for example, 40 ohm cm silicon substrate. The side walls of each of the cells are then implanted 4 times at different twist angles to produce adjacent vertical stripes of alternating N and P concentrations, using appropriate implant dopants for the alternate stripes. This creates, for each well, a self-compensated cell appropriate for use in charge compensation (e.g. superjunction) devices. The wells can be placed closely together, employing a cellular design, with contacts in polysilicon windows located between the wells. A conventional DMOS structure which permits the connection of a source region to the top of one set of wells can be used to turn the device on and off. A conventional guard ring type termination can also be employed in the high resistivity substrate, greatly simplifying the design of the device and its process of manufacture.